RS format

The operand fields of RS-format instructions designate two registers, and a virtual storage address (coded as an implicit address or an explicit address).

┌────────┬────┬────┬────┬────────────┐
│Op Code │ R₁ │ R₃ │ B₂ │     D₂     │
└────────┴────┴────┴────┴────────────┘
0         8   12   16   20          31

In the Insert Characters under Mask (ICM) and the Store Characters under Mask (STCM) instructions, a 4 bit mask (see X'E' and MASK in the instructions labeled DELTA1 and DELTA2 in the examples), with a value 0 - 15, replaces the second register specifications.

┌────────┬────┬────┬────┬────────────┐
│Op Code │ R₁ │ M₃ │ B₂ │     D₂     │
└────────┴────┴────┴────┴────────────┘
0         8   12   16   20          31

Symbols used to represent registers (see REG4, REG6, and BASE in the instruction labeled ALPHA2 in the examples) are assumed to be equated to absolute values 0 - 15.

Symbols used to represent implicit addresses (see AREA and IMPLICIT in the instructions labeled BETA1 and DELTA2 in the examples) can be either relocatable or absolute.

Symbols used to represent displacements (see DISPL in the instruction labeled BETA2 in the examples) in explicit addresses are assumed to be equated to absolute values 0 - 4095.

Many other instruction formats are supported by the High Level Assembler. For complete information see the latest editions of z/Architecture Principles of Operation, SA22-7832 and the z/Architecture Reference Summary, SA22-7871.

Examples:

ALPHA1   LM              4,6,20(12)
ALPHA2   LM              REG4,REG6,20(BASE)
BETA1    STM             4,6,AREA
BETA2    STM             4,6,DISPL(BASE)
GAMMA1   SLL             2,15
DELTA1   ICM             3,X'E',1024(10)
DELTA2   ICM             REG3,MASK,IMPLICIT

When assembled, the object code for the instruction labeled ALPHA1, in hexadecimal, is:

9846C014

where:

98: Is the operation code
4: Is register R₁
6: Is register R₃
C: Is base register B₁
014: Is displacement D₁ from base register B₁

When assembled, the object code for the instruction labeled DELTA1, in hexadecimal, is:

BF3EA400

where:

BF: Is the operation code
3: Is register R₁
E: Is mask M₃
A: Is base register B₁
400: Is displacement D₁ from base register B₁