RR format

The operand fields of RR-format instructions designate two registers, with the following exceptions:

In BCR branching instructions, when a 4 bit branching mask replaces the first register specification (see 8 in the instruction labeled GAMMA1 in the examples).
In SVC instructions, where an immediate value (0 - 255) replaces both registers (see 200 in the instruction labeled DELTA1 in the examples).

┌────────┬────┬────┐
│Op Code │ R₁ │ R₂ │
└────────┴────┴────┘
0         8   12  15

Symbols used to represent registers in RR-format instructions (see INDEX and REG2 in the instruction labeled ALPHA2 in the examples) are assumed to be equated to absolute values 0 - 15.

Symbols used to represent immediate values in SVC instructions (see TEN in the instruction labeled DELTA2 in the examples) are assumed to be equated to absolute values 0 - 255.

Examples:

ALPHA1   LR              1,2
ALPHA2   LR              INDEX,REG2
GAMMA1   BCR             8,12
DELTA1   SVC             200
DELTA2   SVC             TEN

When assembled, the object code of the instruction labeled ALPHA1, in hexadecimal, is:

where:

18: Is the operation code
1: Is register R₁
2: Is register R₂