RI format

The operand fields of RI-format instructions designate a register and an immediate operand, with the following exception:

In BRC branching instructions, a 4 bit branching mask with a value 0 - 15 replaces the register designation.

Symbols used to represent registers (such as REG1 in the example) are assumed to be equated to absolute values 0 - 15. The 16 bit immediate operand has two different interpretations, depending on whether the instruction is a branching instruction or not.

There are two types of non-branching RI-format instructions.

For most, the immediate value is treated as a signed binary integer (-32768 - +32767). This value can be specified by any absolute expression.

┌────────┬────┬────┬─────────────────┐
│Op Code │ R₁ │OpCd│       I₂        │
└────────┴────┴────┴─────────────────┘
0         8   12   16               31

For logical instructions such as TMH, the immediate field is a 16 bit mask.

┌────────┬────┬────┬─────────────────┐
│Op Code │ M₁ │OpCd│       I₂        │
└────────┴────┴────┴─────────────────┘
0         8   12   16               31

Examples:

ALPHA1   AHI             REG1,2000
ALPHA2   MHI             3,1234
BETA1    TMH             7,X'8001'

When assembled, the object code for the instruction labeled BETA1, in hexadecimal, is

A7708001

where:

A7.0: Is the operation code
7: Is register R₁
8001: Is the immediate data I2

For branching RI-format instructions, the immediate value is treated as a signed binary integer representing the number of halfwords to branch relative to the current location.

The branch target can be specified as a relocatable expression, in which case the assembler performs some checking, and calculates the immediate value.

The branch target can also be specified as an absolute value, in which case the assembler issues a warning before it assembles the instruction.

Examples:

ALPHA1   BRAS            1,BETA1
ALPHA2   BRC             3,ALPHA1
BETA1    BRCT            7,ALPHA1

When assembled, the object code for the instruction labeled BETA1, in hexadecimal, is

A776FFFC

where:

A7.6: Is the operation code
7: Is register R₁
FFFC: Is the immediate data I2; a value of -4 decimal

If the GOFF assembler option is active, then it is possible to specify the target address as one or more external symbols (with or without offsets).

If an offset is specified it can be specified as an absolute or relocatable expression. If the offset is specified as a relocatable expression, the assembler performs some checking and calculates the immediate value. If the offset is an absolute expression the assembler issues warning message ASMA056W.

Examples:

        ALPHA1 BRAS    14,A-B+C+10  where A, B and C are external symbols
        ALPHA2 BRASL   14,A-B+C+10
        BETA1  BRC     15,A-B+C+10

When assembled, the object code for the instruction labeled BETA1, in hexadecimal, is

A7F40005

where:

        A7.4 is the operation code
        F    is the condition code
        0005 is the immediate data I2; a value of 5 decimal.

In addition GOFF Relocation Dictionary Data Items are generated for the external symbols A, B, and C.