EXCP and EXCPVR Appendages

An appendage is a routine that provides additional control over I/O operations. Using appendages, you can examine the status of I/O operations and determine the actions to be taken for various conditions. An appendage can receive control as shown in Table 1.

Table 1. EXCP Appendages
Appendage	Description	When Called
ABE	Abnormal-end	Abnormal conditions
CHE	Channel-end	Channel-end, unit exception, wrong-length record
EOE	End-of-extent	DASD track address in I/O block outside allocated extent limits
PCI	Program-controlled interruption	When one or more PCI bits are on in a channel program
PGFX	Page-fix	Prior to SIO for EXCPVR requests
SIO	Start-I/O	Just prior to translating channel program

Appendages get control in supervisor state, protection key 0, receiving the pointers from the system described in the following table. The appendages receive control in 24-bit addressing mode and must return in the same mode.

This information is not part of the intended interface.

Register: Content
0: Points to the user's IOBE if one was provided as input to EXCP or EXCPVR. Otherwise 0 is passed to the appendage routine.
1: Points to the request queue element.
2: Points to the input/output block.
3: Points to the data extent block.
4: Points to the data control block.
6: Points to the seek address (MBBCCHHR) if control is given to an end-of-extent appendage.
The track address of the block reference (CCHH) may contain 28-bit cylinder numbers for devices with more than 65,520 cylinders. Showing nibbles it is in the form of CCCCcccH, where ccc represent bits 0-11 of the 28-bit cylinder number and CCCC represents bits 12-27 the 28-bit cylinder number. Use the TRKADDR macro to manipulate 16-bit and 28-bit cylinder numbers correctly.
7: Points to the unit control block (UCB) and always contains a clean 31–bit UCB address. If the DEB flag "DEB31UCB" is off, then the UCB address is captured below the 16 MB line. Whereas if DEB31UCB is on, then the address might point above the 16 MB line even though the appendages always are entered in 24–bit mode. The UCB address is captured by OPEN or EOV until EOV or CLOSE uncaptures it. If the DCBE option "LOC" was not set or defaulted to "BELOW", that is LOC=BELOW or not coded, or the "NON_VSAM_XTIOT" option of the DEVSUPxx member of PARMLIB was set or defaulted to "NO", that is NON_VSAM_XTIOT=NO or not coded. In other words, OPEN does not capture the UCB if LOC and NON_VSAM_XTIOT were specified as follows: LOC=ANY and NON_VSAM_XTIOT=YES.
13: Points to a 16-word area you can use to save input registers or data.
14: Points to the location in the system where control is to be returned following execution of an appendage. When returning control to the system, you can use displacements from the return address in register 14. Allowable displacements are summarized and described later for each appendage in Table 2.
15: Points to the entry point of the appendage. When the PGFX appendage is entered, points to the SIO entry point.

The processing done by appendages is subject to the following requirements and restrictions:

Register 9, if used, must be set to binary zeros before control is returned to the system. All other registers, except those indicated in the descriptions of the appendage, must be saved and restored if you use them. Table 2 summarizes register conventions. Note that the need to save and restore registers applies to all eight byes in each register.
No SVC instructions or instructions that change the status of the system (for example, WTO, LPSW, or similar privileged instructions) can be issued.
Loops testing for the completion of I/O operations cannot be used.

The information here describes appendage types, with explanations of when they are entered, how they return control to the system, and which registers they can use without saving and restoring their contents. If you do not supply a particular appendage, or supply no appendage, the system acts as though that appendage had returned at offset 0 from register 14.

Table 2. Entry Points, Returns, and Available Work Registers for Appendages
Appendage	Entry Point	Returns	Available Work Registers
EOE	Reg 15	Reg 14 + 0 - Call ABE Reg 14 + 4 - Skip Reg 14 + 8 - Try again	Reg. 10, 11, 12, and 13
SIO	Reg 15	Reg 14 + 0 - Normal Reg 14 + 4 - Skip	Reg. 10, 11, and 13
PCI	Reg 15	Reg 14 + 0 - Normal	Reg. 10, 11, 12, and 13
PGFIX	Reg 15+4	Reg 14 + 0 - Normal	Reg. 10, 11, and 13
CHE	Reg 15	Reg 14 + 0 - Normal Reg 14 + 4 - Skip Reg 14 + 8 - Re-EXCP Reg 14 + 12 - By pass	Reg. 10, 11, 12, and 13
ABE	Reg 15	Reg 14 + 0 - Normal Reg 14 + 4 - Skip Reg 14 + 8 - Re-EXCP Reg 14 + 12 - By pass	Reg. 10, 11, 12, and 13
Note: The register conventions for passing parameters from appendages to the system are described in the individual appendage descriptions.