Closed as program error.
See Problem Summary.
APAR NUMBER: PJ37995 PRODUCT: z/TPF FUNCTIONAL AREA: INITIALIZATION SHIPPED IN PUT: 10 ABSTRACT: Allow 64-bit programs to run in 2-4GB address range to improve system performance. PACKAGE CONTENTS: Source Segments: (C) base/cp/chsz.cpy (C) base/cp/cpse.cpy (C) base/cp/cpsl.cpy (C) base/cp/ct38.cpy (C) base/cp/ct40.cpy (C) base/cp/cth4.cpy (C) base/cp/ctin.cpy (C) base/cp/cudu.cpy (C) base/exp/CTAL.exp (C) base/include/tpf/c_eb0eb.h (C) base/include/tpf/sysapi.h (C) base/macro/ieqce2.mac (C) base/ol/ib01.cpy (C) base/rt/collatetrace.c (C) base/rt/cudapt.cpp (C) base/rt/cudask.cpp (C) base/rt/cvxs.c (C) base/rt/cvzi.asm (C) base/rt/trap_write.c Object Only Binaries: None. Configuration Independent Binaries: (C) base/lib/libCTPW.so (C) base/lib/libCUDA.so (C) base/lib/libCVXS.so (C) base/load/CTPW.so (C) base/load/CUDA.so (C) base/load/CVXS.so (C) base/load/CVZI.so (C) base/obj/cudapt.o (C) base/obj/cudask.o (C) base/obj/cvxs.o (C) base/obj/cvzi.o (C) base/obj/trap_write.o Support Files: base/lst/cudapt.lst base/lst/cudask.lst base/lst/cvxs.lst base/lst/cvzi.lst base/lst/CTPW.map base/lst/CUDA.map base/lst/CVXS.map base/lst/CVZI.map base/lst/trap_write.lst OTHER BINARIES TO BUILD: YES (C) <sys>/load/CPS0.so (C) <sys>/load/IPLB.so (C) <sys>/obj/cccpse.o (C) <sys>/obj/ccctin.o (C) <sys>/obj/ccnucl.o (C) <sys>/obj/ccthds.o (C) <sys>/obj/ccvage.o (C) <sys>/obj/collatetrace.o (C) <sys>/obj/iplb.o (C) <sys>/stdlib/libCTAL.so (C) <sys>/stdload/CTAL.so (C) os390/bin/ppcp.pds (C) os390/obj/ccmcdc.o (C) os390/obj/stpp.o COMMENTS: Address the following issues: 1.Placing z/TPF 64-bit programs in the 2-4GB virtual address range allows certain systems to see a performance gain from improved branch prediction processing for programs executing within either of the 64-bit CRPAs. 2.Update the following support areas that have specific checks that assume all addresses in 2-4GB range are not valid program addresses: Debugger support Performance Analyzer support Software Profiler support ZIDOT CREATE command processing ZDECB NEST command processing Online ECB trace formatting 3.Remove the following obsolete ECB page 2 fields: CE2SGCRP64, CE2PGCRP64, CE2SG1MB, CE2PGH31, CE2SGH64, CE2PGH64, CE2SDPGS, CE2SDTIM, CE2SDCNT, and CE2SDRESV. The information previously held in these fields was moved to the ECB process block fields such as IPROC_SGCRPA64 and IPROC_PGCRPA64. 4.Update various parts of dump processing to handle program addresses in the 2-4GB address range. Correct bug in dump override extensions processing that incorrectly sets up PFXERSVA (ECB SVM and EVM address fields) from ECB page 1 when the required information is actually in ECB page 2.
SOLUTION: In order to allow for valid virtual addresses from 2-4GB the following changes were required: ib01.cpy (IPLB) - Build a SVM segment table for addresses 2-4GB. ctin.cpy - After calling CT38 routine, check if 64-bit CRPAs were allocated in 2-4GB range. If not, issue warning message to console. ct38.cpy (CCCTIN csect) - Check if the combined size of the 2 64-bit CRPAs fits in the 2-4GB address range. There will be no overlap of 31-bit CRPA addresses and 64-bit CRPA addresses in terms of their offset into their specific 2GB range. To guarantee no overlap, the 64-bit CRPAs will be placed in the 2-4GB range starting at an offset that equals then ending address of the 31-bit copy-on-write CRPA. This means that the combined size of the 64-bit CRPAs must be less than or equal to the following: 2GB - <ending address of 31-bit copy-on-write CRPA>. The 64-bit standard CRPA is allocated first in the 2-4GB range, followed by the 64-bit c-o-w CRPA. Memory configuration storage calculations in routine MCMEMREQ has been updated to include storage required for all ECBs having an additional 16KB segment table to map addresses in the 2-4GB range. ct40.cpy (CCCTIN csect) - Allocate additional segment table for 2-4GB EVM address range. If 64-bit CRPAs are in 2-4GB range, handle setting up EVM 64-bit copy-on-write CRPA page tables. Update DSTOC macro service routine to handle putting 64-bit CRPAs in 2-4GB range. Update INITEVMDAT routine to set up each ECB's EVM second region third entry with segment table address for 2-4GB. cth4.cpy (CCTHDS csect) - Update CTH4CLHV routine to handle initializing 64-bit copy-on-write DAT table entries, if the CRPA is in the 2-4GB range, for an ECB that was previously a thread ECB. cpse.cpy (CCCPSE csect) - Update dump formatting to eliminate bit 32 being set in last 10 branch trace entries display when branch address actually resides in 0-2GB address range. Now bit 32 is only set for branch addresses in the 2-4GB address range. cpsl.cpy (CCCPSE csect) - Update dump formatting for ECB stack frame formatting to detect program linkage addresses in the 2-4GB address range. Update macro trace entry pre-formatting routine CPSLMFMT to handle program addresses in the 2-4GB address range. Update dump extension processing to correct an error below label DECBOK that was incorrectly setting up PFXERVAS fields from ECB page 1 rather than ECB page 2 field CE2VAS. cudu.cpy (CCVAGE csect) - Update performance analyzer routine CUDPAWR to detect an event address in the 2-4GB address range. cvxs.c (ZDECB NEST) - Update ZDECB NEST processing to detect program linkage addresses that are in the 2-4GB address range. cvzi.asm (ZIDOT CREATE) - Allow creation of a dump override that resides in 2-4GB address range if the dump override addresses reside in 64-bit CRPAs. cudapt.cpp (Debugger support) - Update debugger support routine UDUT_VerifyPatAddress() to detect program address in 2-4GB address range when 64-bit CRPAs are in that address range. cudask.cpp (Debugger support) - Update debugger support routine UDSK_GetReturnAddr() to handle program return address that resides in the 2-4GB address range. trap_write.c (Software Profiler support) - Update profiler support code to detect program linkage addresses in the 2-4GB address range. cformattrace.cpp (Trace formatting) - Update tracing support code to detect program linkage addresses in the 2-4GB address range. COREQS: NO None. MIGRATION CONSIDERATIONS: YES Functional, automation, and operation changes: New message: CT380001W Performance or tuning changes: This SPE can provide performance improvement on systems that have a high amount of program execution within either of the 64-bit CRPAs (typically C/C++ programs). BUILD COMMANDS AND INSTRUCTIONS: YES #maketpf commands for linux maketpf -f CTAL collatetrace.o maketpf -f CPS0 cccpse.o ccctin.o ccnucl.o ccthds.o ccvage.o maketpf -f IPLB iplb.o maketpf -f CVZI cvzi.o maketpf -f CVXS cvxs.o maketpf -f CUDA cudapt.o cudask.o maketpf -f CTPW trap_write.o maketpf CTAL link TPF_VERIFY_LINK_REFS=NO maketpf CPS0 link maketpf IPLB link maketpf CVZI link maketpf CVXS link maketpf CUDA link TPF_VERIFY_LINK_REFS=NO maketpf CTPW link TPF_VERIFY_LINK_REFS=NO maketpf CTAL link maketpf CUDA link maketpf CTPW link #maketpf commands for z/OS maketpf -f ppcp ccmcdc.o stpp.o maketpf ppcp link UPDATED INFORMATION UNITS: YES z/TPF and z/TPFDF Migration Guide z/TPF and z/TPFDF Migration Guide: PUT 2 and Later z/TPF and z/TPFDF System Generation z/TPF Concepts and Structures z/TPF Main Supervisor Reference z/TPF Messages (Online, SQLCODEs, and errno Values) z/TPF Program Development Support Reference See your IBM representative if you need additional information. DOWNLOAD INSTRUCTIONS: http://www.ibm.com/software/htp/tpf/maint/maintztpf.html APAR URL: http://www.ibm.com/software/htp/tpf/ztpfmaint/put10/PJ37995.htm
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