mtfsf (Move to FPSCR Fields) instruction

Purpose

Copies the contents of a floating-point register into the Floating-Point Status and Control Register under the control of a field mask.

Syntax

See Extended Mnemonics of Condition Register Logical Instructions for more information.

Description

The mtfsf instruction copies bits 32-63 of the contents of the floating-point register (FPR) FRB into the Floating-Point Status and Control Register under the control of the field mask specified by FLM.

The field mask FLM is defined as follows:

Bit   Description

7   FPSCR 00-03 is updated with the contents of FRB 32-35.

8   FPSCR 04-07 is updated with the contents of FRB 36-39.

9   FPSCR 08-11 is updated with the contents of FRB 40-43.

10   FPSCR 12-15 is updated with the contents of FRB 44-47.

11   FPSCR 16-19 is updated with the contents of FRB 48-51.

12   FPSCR 20-23 is updated with the contents of FRB 52-55.

13   FPSCR 24-27 is updated with the contents of FRB 56-59.

14   FPSCR 28-31 is updated with the contents of FRB 60-63.

The mtfsf instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.

The two syntax forms of the mtfsf instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Note: When specifying FPSCR 0-3, some bits cannot be explicitly set or reset.

Parameters

Examples

1. The following code copies the contents of floating-point register 5 bits 32-35 into Floating-Point Status and Control Register Field 0:

   
   # Assume bits 32-63 of FPR 5
   # contain 0x3000 3000.
   mtfsf 0x80,5
   # Floating-Point Status and Control Register
   # Field 0 is set to b'0001'.
   

2. The following code copies the contents of floating-point register 5 bits 32-43 into Floating-Point Status and Control Register Fields 0-2 and sets Condition Register Field 1 to reflect the result of the operation:

   
   # Assume bits 32-63 of FPR 5
   # contains 0x2320 0000.
   mtfsf. 0xE0,5
   # Floating-Point Status and Control Register Fields 0-2
   # now contain b'0010 0011 0010'.
   # Condition Register Field 1 now contains 0x2.