dcbf (Data Cache Block Flush) instruction

Purpose

Copies modified cache blocks to main storage and invalidates the copy in the data cache.

Note: The dcbf instruction is supported only in the PowerPC® architecture.

Syntax

Description

The dcbf instruction calculates an effective address (EA) by adding the contents of general-purpose register (GPR) RA to the contents of GPR RB. If the RA field is 0, EA is the sum of the contents of RB and 0. If the cache block containing the target storage locations is in the data cache, it is copied back to main storage, provided it is different than the main storage copy.

Consider the following when using the dcbf instruction:

• If a block containing the byte addressed by the EA is in the data cache and has been modified, the block is copied to main memory. If a block containing the byte addressed by EA is in one of the caches, the block is made not valid.
• If the EA specifies a direct store segment address, the instruction is treated as a no-op.

The dcbf instruction has one syntax form and does not effect the Fixed-Point Exception Register.

Parameters

Examples

The software manages the coherency of storage shared by the processor and another system component, such as an I/O device that does not participate in the storage coherency protocol. The following code flushes the shared storage from the data cache prior to allowing another system component access to the storage:

# Assume that the variable A is assigned to storage location
# 0x0000 4540.
# Assume that the storage location to which A is assigned
# contains 0.
# Assume that GPR 3 contains 0x0000 0040.
# Assume that GPR 4 contains 0x0000 4500.
# Assume that GPR 5 contains -1.
st      R5,R4,R3         # Store 0xFFFF FFFF to A
dcbf    R4,R3            # Flush A from cache to main memory
sync                     # Ensure dcbf is complete. Start I/O
                         # operation

After the store, but prior to the execution of the dcbf and sync instructions, the copy of A in the cache contains a -1. However, it is possible that the copy of A in main memory still contains 0. After the sync instruction completes, the location to which A is assigned in main memory contains -1 and the processor data cache no longer contains a copy of location A.