The example below shows a sample of the machine state block.
Note:
- After program checks, if the TRAP(ON,NOSPIE) and ALL31(OFF) runtime options are in effect, the HR_VALID flag bit in the Machine State FLAGS field will be off; this indicates that the saved high registers are not valid. After ABENDs, if the ALL31(OFF) runtime option is in effect, the HR_VALID flag bit in the Machine State FLAGS field will be off; this indicates that the saved high registers are not valid.
- If a nested enclave ends because of an unhandled condition and a 4094-40 ABEND is declared, the high registers may not be valid in the Machine State that contains information about the 4094-40 ABEND.
- If an ABEND occurs or a program check occurs with the TRAP(ON,NOPSPIE) runtime option in effect, and the SDWA registers at the time of interrupt (in the SDWAGRSV field) are not appropriate or recognizable, and Language Environment® instead saves the registers from the SDWASRSV field in the Machine State, the high registers may not be valid in the Machine State.
OFFSETS
DEC HEX TYPE LEN NAME (DIM) DESCRIPTION
-------------------------------------------------------------------------------
0 (0) STRUCTURE 512 MCH Lang Env Machine State
0 (0) CHARACTER 4 MCH_EYE Eye Catcher
4 (4) SIGNED 2 MCH_SIZE Size of area
6 (6) SIGNED 2 MCH_LEVEL Level of generation
8 (8) CHARACTER 64 REG GPR at interrupt
8 (8) SIGNED 4 GPR (0:15) Individual regs
72 (48) CHARACTER 8 PSW Basic or extended PSW at
time of interrupt
80 (50) SIGNED 4 INTI EPIE Fields - ILC & code
80 (50) SIGNED 2 ILC Extended PSW ILC
82 (52) SIGNED 2 IC Extended PSW interrupt
82 (52) UNSIGNED 1 IC1 1st byte of Ext
PSW Int code
83 (53) UNSIGNED 1 IC2 2nd byte of Ext
PSW Int code
84 (54) ADDRESS 4 PFT Page fault location
88 (58) CHARACTER 32 FLT Float regs
88 (58) CHARACTER 8 FLT_0 Floating point reg 0
96 (60) CHARACTER 8 FLT_2 Floating point reg 2
104 (68) CHARACTER 8 FLT_4 Floating point reg 4
112 (70) CHARACTER 8 FLT_6 Floating point reg 6
120 (78) BITSTRING 44 * (reserved)
164 (A4) ADDRESS 4 INT_SF Interrupt stack frame
168 (A8) BITSTRING 11 * (reserved)
179 (B3) BITSTRING 1 FLAGS MCH flags
.1.. .... HR_VALID HI regs saved in MCH
..1. .... INT_SF_VALID "X'20'" Interrupt stackframe
valid in INT_SF field
...1 .... SAVSTACK "X'10'" CEECAA_SAVSTACK field
was set to the value in INT_SF
field at interrupt time
.... 1... SAVSTACK_ASYNC
"X'08'" CEECAA_SAVSTACK_ASYNC
field pointed to a field that
was set to the value in INT_SF
field at interrupt time
.... .1.. AR_VALID Access registers saved in MCH
.... ..1. VR_VALID Vector registers saved in MCH
1... ...1 * Internal flags
180 (B4) BITSTRING 4 * (reserved)
184 (B8) ADDRESS 4 MCH_EXT Ptr to language MCH extension
188 (BC) BITSTRING 4 MCH_BEA Copy of SDWA_BEA
192 (C0) ADDRESS 4 SAVSTACK_ASYNC_PTR
Value in CEECAA_SAVSTACK_ASYNC
field at time of interrupt
(for debugging purposes only)
196 (C4) BITSTRING 12 * (reserved)
208 (D0) CHARACTER 104 AFP Additional FP regs
208 (D0) CHARACTER 8 FLT_1 Floating point reg 1
216 (D8) CHARACTER 8 FLT_3 Floating point reg 3
224 (E0) CHARACTER 8 FLT_5 Floating point reg 5
232 (E8) CHARACTER 8 FLT_7 Floating point reg 7
240 (F0) CHARACTER 8 FLT_8 Floating point reg 8
248 (F8) CHARACTER 8 FLT_9 Floating point reg 9
256 (100) CHARACTER 8 FLT_10 Floating point reg 10
264 (108) CHARACTER 8 FLT_11 Floating point reg 11 272 (110) CHARACTER 8 FLT_12 Floating point reg 12
280 (118) CHARACTER 8 FLT_13 Floating point reg 13
288 (120) CHARACTER 8 FLT_14 Floating point reg 14
296 (128) CHARACTER 8 FLT_15 Floating point reg 15
304 (130) CHARACTER 4 FPC FP control register
1... .... FPC_IMI IEEE Invalid operation mask
.1.. .... FPC_IMZ IEEE Divide by zero mask
..1. .... FPC_IMO IEEE Overflow mask
...1 .... FPC_IMU IEEE Underflow mask
.... 1... FPC_IMX IEEE Inexact mask
.... .111 FPC_RS0 Byte 0 reserved bits
305 (131) 1... .... FPC_SFI IEEE Invalid
operation flag
.1.. .... FPC_SFZ IEEE Divide by zero flag
..1. .... FPC_SFO IEEE Overflow flag
...1 .... FPC_SFU IEEE Underflow flag
.... 1... FPC_SFX IEEE Inexact flag
.... .111 FPC_RS1 Byte 1 reserved bits
306 (132) BITSTRING 1 FPC_DXC Data Exception Code
307 (133) 1111 11.. FPC_RS3 Byte 3 reserved bits
.... ..11 FPC_RM Rounding Mode
308 (134) BITSTRING 1 _AFP_FLAGS AFP flag byte
1... .... AFP_SAVED FPRs 1,3,5,7,8-15 were
saved in MCH
309 (135) CHARACTER 11 RSV2 reserved
320 (140) CHARACTER 64 REG_H GPR-hi at interrupt
320 (140) SIGNED 4 GPR_H (0:15) Individual regs
384 (180) CHARACTER 64 AREG Access registers
384 (180) SIGNED 4 AR(0:15) Individual access registers
448 (1C0) CHARACTER 64 RSV3 reserved
512 (200) CHARACTER 512 VREG Vector registers
512 (200) CHARACTER 16 VR (0:31) Individual vector registersThe code example (below) shows the cross reference summary of the machine state block.
HEX HEX
NAME OFFSET VALUE LEVEL
MCH 0 1
_AFP_FLAGS 134 2
AFP_SAVED 134 80 3
APF D0 2
AR_VALID B3 04 3
AR(0:15) 180 3
AREG 180 2
FLAGS B3 00 2
FLT 58 2
FLT_0 58 3
FLT_1 D0 3
FLT_10 100 3
FLT_11 108 3
FLT_12 110 3
FLT_13 118 3
FLT_14 120 3
FLT_15 128 3
FLT_2 60 3
FLT_3 D8 3
FLT_4 68 3
FLT_5 E0 3
FLT_6 70 3
FLT_7 E8 3
FLT_8 F0 3
FLT_9 F8 3
FPC 130 3
FPC_DXC 132 4
FPC_IMI 130 80 4FPC_IMO 130 20 4
FPC_IMU 130 10 4
FPC_IMX 130 08 4
FPC_IMZ 130 40 4
FPC_RM 133 0X 4
FPC_RS0 130 0X 4
FPC_RS1 131 0X 4
FPC_RS3 133 XX 4
FPC_SFI 131 80 4
FPC_SFO 131 20 4
FPC_SFU 131 10 4
FPC_SFX 131 08 4
FPC_SFZ 131 40 4
GPR(0:15) 8 3
GPR_H(0:15) 140 3
HR_VALID B3 40 3
IC 52 3
IC1 52 4
IC2 53 4
ILC 50 3
INTI 50 2
INT_SF A4 2
INT_SF_VALID B3 20 3
MCH_BEA BC 00000000 2
MCH_EXT B8 2
MCH_EYE 0 2
MCH_LEVEL 6 2
MCH_SIZE 4 2
PFT 54 4
PSW 48 2
REG 8 2
REG_H 140 2
RSV2 135 2
RSV3 1C0 2
SAVSTACK B3 10 3
SAVSTACK_ASYNC B3 8 3
SAVSTACK_ASYNC_PTR C0 2
VR_VALID B3 02 3
VR(0:31) 200 3
VREG 200 2