Registers

You can specify a register in an operand for use as an arithmetic accumulator, a base register, an index register, and as a general depository for data to which you want to refer repeatedly.

You must be careful when specifying a register whose contents have been affected by the execution of another machine instruction, the control program, or an IBM-supplied system macro instruction.

For some machine instructions, you are limited in which registers you can specify in an operand.

The expressions used to specify registers must have absolute values; in general, registers 0 through 15 can be specified for machine instructions. However, the following restrictions on register usage apply:

The even-numbered registers must be specified for the following groups of instructions:
- The double-shift instructions
- Most multiply and divide instructions
- The move long and compare logical long instructions
If the NOAFPR ACONTROL operand is specified, then only the floating-point registers (0, 2, 4, or 6) can be specified for floating-point instructions.
If the AFPR ACONTROL operand is specified, then one of the floating-point registers 0, 1, 4, 5, 8, 9, 12, or 13 can be specified for the instructions that use extended floating-point data in pairs of registers, such as AXR, SXR, LTXBR, and SQEBR.
If the NOAFPR ACONTROL operand is specified, then either floating-point register 0 or 4 must be specified for these instructions.
For a processor with a vector facility, the even-numbered vector registers (0, 2, 4, 6, 8, 10, 12, 14) must be specified in vector-facility instructions that are used to manipulate long floating-point data or 64 bit signed binary data in vector registers.

The assembler checks the registers specified in the instruction statements of the above groups. If the specified register does not comply with the stated restrictions, the assembler issues a diagnostic message and does not assemble the instruction. Binary zeros are generated in place of the machine code.