Controlling sequence of access to resources

If you want a resource to be accessed by two or more tasks in a specific order, instead of ENQ and DEQ commands, use one or more WAITCICS commands with one or more hand-posted ECBs.

To hand-post an ECB, a CICS® task sets a 4 byte field to either the cleared state of binary zeros, or the posted state of X'40008000'. The task can use a START command to start another task and pass the address of the ECB. The started task receives the address through a RETRIEVE command.

Either task can set the ECB or wait on it. Use the ECB to control the sequence in which the tasks access resources. Two tasks can share more than one ECB if necessary. You can extend this technique to control as many tasks as you want.

Note: Only one task can wait on a given ECB at any one time.

The example in Figure 1 shows how two tasks can sequentially access a temporary storage queue by using hand-posted ECBs and a WAITCICS command.

The example uses two ECBs, (ECB1 and ECB2), addressed by the pointers illustrated in Figure 2.

In theory, these tasks could exchange data through the temporary storage queue for ever. In practice, some code would be included to close down the process in an orderly way.

Figure 1. Two tasks using WAITCICS to control access to a shared resource
Task A                                          Task B
Delete temporary storage queue
Clear ECB1 (set to X'00000000')
Clear ECB2
EXEC CICS START task B ( pass addresses         EXEC CICS RETRIEVE
of PTR_ECB1_ADDR_LIST and                         (addresses passed)
PTR_ECB2_ADDR_LIST

LOOP:                                           LOOP:
 EXEC CICS WAITCICS                              Write to TS queue
  ECBLIST(PTR_ECB1_ADDR_LIST)                    Post ECB1 (set to X'40008000)
  NUMEVENTS(1)                                   EXEC CICS WAITCICS
 Clear ECB1                                       ECBLIST(PTR_ECB2_ADDR_LIST)
 Read TS queue                                    NUMEVENTS(1)
 Process data                                     
 Delete TS queue                                  
 Write to TS queue  
 Post ECB2                                       ClearECB2
Go to start of loop                              Read TS queue
                                                 Process data
                                                 Delete TS queue
                                                 Go to start of loop                                  
Figure 2. ECB pointers used by WAITCICS example
Diagram showing PTR_ECB1_ADDR_LIST containing the address of ECB1_ADDR_LIST, which. contains the address of ECB1. PTR_ECB2_ADDR_LIST contains the address of ECB2_ADDR_LIST, which contains the address of ECB2.

Dealing with exception conditions describes how the exception conditions that can occur during processing of a task control command are handled.



dfhp37r.html | Timestamp icon Last updated: Thursday, 27 June 2019