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PowerPC 476FP and PLB6 Caching and Coherency Guidelines
Related links: PowerPC 476FP Embedded Core

Application Note
This application note describes simplified options that provide effective and efficient caching and coherency support implemented in hardware for a multiple PowerPC 476FP SoC implementation. These options let you specify the set of caching and coherency attributes defined by the Power Architecture®. You can also specify how the options apply to various memory and I/O devices in a typical processor-based chip implementation.

Revision Date: 04/26/13

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PowerPC 476FP and PLB6 Caching and Coherency GuidelinesPDF89 KB
 

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