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JTAG TAP Controller with PowerPC 4xx Cores
Related links: PowerPC 405 Embedded Cores, PowerPC 440 Embedded Core, PowerPC 464 H90 Embedded Core, PowerPC 464FP H65 Embedded Core, PowerPC 464FP H90 Embedded Core, PowerPC 476FP Embedded Core, PowerPC Cores

Application Note
This application note explains how to use a connections file to integrate the PowerPC 4xx JTAG TAP controller logic into the chip level. It provides examples of the BSDL_INLINE/JTAG_INLINE section of an IOSpeclist file, which is used to verify the PowerPC 4xx core in the IEEE 1149.1 standard using the Cadence Encounter Test tool. It also provides the syntax used to write the RISCWatch processor configuration file (PCF) in a multiple-cores environment to select a specific core for debug.

Revision Date: 09/26/12

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JTAG TAP Controller with PowerPC 4xx Cores Application NotePDF140 KB

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