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On-Chip Peripheral Bus
Related links: CoreConnect Bus Architecture

Specifications
This book begins with an overview followed by detailed information on On-Chip Peripheral Bus signals, interfaces, timing and operations. This book is for hardware, software, and application developers who need to understand Core+ASIC development and system-on-a-chip (SOC) designs. The audience should understand embedded system design, operating systems, and the principles of computer organization.

Publication Number: SA-14-2528-02

Revision Date: 04/01/01

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OpbBus.pdfPDF1M
 

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