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PowerPC 476FP L2 Cache Core Databook
Related links: PowerPC 476FP Embedded Core

The IBM PowerPC 476FP L2 Cache Core contains the second-level cache that manages transfers between the PowerPC 476FP L1 instruction and data caches and the Processor Local Bus 6 (PLB6) interconnect of a multicore coherent memory subsystem. This document provides information about the registers, facilities, initialization, and use of the PowerPC 476FP L2 cache core.

Revision Date: 11/08/11

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PowerPC 476FP L2 Cache Core DatabookPDF3330 KB

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