IBM®
Skip to main content
    Country/region [select]      Terms of use
 
 
   
     Home      Products      Services & solutions      Support & downloads      My account     
CoreConnect Bus Architecture
Related links: CoreConnect Bus Architecture

White Paper
This white paper describes CoreConnectâ„¢ Bus Architecture, a 32-, 64-, 128-bit core on-chip bus standard that eases the integration and reuse of processor, system, and peripheral cores within standard product and custom system-on-a-chip (SOC) designs. Topics include Processor Local Bus, PLB Bus Transactions, PLB Cross-Bar Switch, On-Chip Peripheral Bus, OPB Bridge, OPB Implementation, DCR Bus, Design Toolkits, and comparison to other bus architecture types. Block and timing diagrams are included. Eight pages.

Revision Date: 09/01/99

LinkFile typeSize
crcon_wp.pdfPDF52K
 

IBM Customer Connect
Sign in  

IBM microNews
  Feedback
Questions or comments on the technical library
  Help
Information on search and navigation

    About IBM Privacy Contact