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CoreConnect Bus Architecture
Related links: CoreConnect Bus Architecture

Product Brief
This product brief describes CoreConnect™ Bus Architecture, a 32-, 64-, 128-bit core on-chip bus standard that eases the integration and reuse of processor, system, and peripheral cores within standard product and custom system-on-a-chip (SOC) designs. Topics include Processor Local Bus, On-Chip Peripheral Bus, PLB Arbiter, PLB to OPB Bridge, OPB to PLB Bridge, OPB Arbiter, DCR Bus, Bus Model Toolkits, and Licensing Information. Block diagram and technical specifications are included. Two pages.

Publication Number: GK10-3116-00

Revision Date: 09/01/99

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