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SPU Instruction Set Architecture

The Cell Broadband Engine architecture defines a single-chip multiprocessor consisting of one or more Power Processor Elements (PPEs) and multiple high-performance Synergistic Processor Elements (SPEs). The Synergistic Processor Unit (SPU) is part of the SPE in the Cell Broadband Engine Processor. The SPU instruction set architecture (ISA) provides 7-bit register operand specifiers to directly address 128 registers using a pervasive single instruction, multiple data (SIMD) computation approach for both scalar and vector data. This specification describes the SPU Instruction Set Architecture.

Revision Date: 01/27/07

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SPU Instruction Set ArchitecturePDF3.3 MB

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