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PowerPC 476FP, L2 Cache Controller, and PLB6 Arbiter Signal Connections Application Note
Related links: PowerPC 476FP Embedded Core

Application Note
This application note describes the minimum connections between two Cu-45HP PowerPC 476FP hard cores, their L2 cache controllers, and a peripheral local bus arbiter, version 6 (PLB6 arbiter).

Revision Date: 01/25/11

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PowerPC 476FP, L2 Cache Controller, and PLB6 Arbiter Signal Connections Application NotePDF86 KB
 

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