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PowerPC 470S Synthesizable Core
Related links: PowerPC Cores

The IBM® PowerPC® 470S synthesizable core is intended for use in PowerPC-based system-on-a-chip (SoC) implementations. As a synthesizable core, the PowerPC 470S supports fabrication in multiple foundries. It allows the SoC designer to select the cache size and processor local bus (PLB) version necessary to optimize single processor and cache-coherent multiprocessor SoC designs. The 470S design flexibility and scalability meet the performance and power demands of a range of applications from digital TVs to highly parallel, high-performance computers.

The PowerPC 470S core is a 4-issue processor with a 9-stage, 5-pipeline integer unit and a 12-stage, 2-pipeline floating-point unit. Memory management is optimized for multitasking embedded environments and symmetric multiprocessor systems. Additional functions include cache control, power control, timers, and debug facilities. Companion cores include an L2 cache controller that supports memory coherency, a PLB controller that supports coherent and noncoherent functional blocks, and a DDR3 memory controller with coherency support.

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(Click on column header to sort)
!PowerPC 470S Synthesizable Core DatabookDatabook06/23/15
!PowerPC 476FP and 470S Core Errata NoticeErrata Notice09/22/14
PowerPC 476FP Embedded Processor Core User's ManualUser Guide07/31/14
!Implementing the Branch Workaround for PowerPC 47x Erratum #46Application Note04/23/14
!Implementing Two 512KB Cache Controllers for PowerPC 476FP for 1MB L2 Cache ApplicationsApplication Note01/25/12
!PowerPC 476FP L2 Cache Controller (ASIC Version)Errata Notice10/05/11
Multiprocessor Interrupt Controller Data BookDatabook05/16/11
PowerPC 470S and 476FP Technical OverviewPresentation02/15/11
!Multiprocessor Interrupt Controller Errata NoticeErrata Notice10/25/10
Multiprocessor Interrupt Controller (MPIC)Product Overview03/02/06

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