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PowerPC 460S Embedded Core
Related links: PowerPC Cores

As a synthesizable core the 460S provides the flexibility of fabrication in multiple foundries. The 460S core allows the SoC designer to select the size cache and Processor Local Bus (PLB) version necessary to optimize single processor and cache coherent multi-processor SoC designs. The 460S design flexibility and scalability will meet the performance and power demands of today’s communications, consumer electronics and storage embedded applications.

The 460S contains a dual-issue, superscalar, pipelined processing unit. The core includes memory management, cache control, timers and debug facilities. Interfaces for custom co-processors and floating point functions are provided, along with separate instruction and data cache array interfaces which can be configured to various sizes.

For more information on PowerPC Licensing, please click here.

(Click on column header to sort)
Optimized Code Using DSP Instructions for PowerPC 4xxApplication Note04/17/08
Optimizing PowerPC 440 and PowerPC 464 Memory Copy RoutinesApplication Note01/18/08
PowerPC 460SProduct Overview10/16/06
PPC460-S Embedded Processor CoreUser Guide10/14/10
Routing Debug halt and Trace Signals with Multi-PPC405 Core DesignsApplication Note02/27/07
Using the New PPC4xx Indexed DCR Access InstructionsApplication Note06/15/08

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