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PowerPC 440 Embedded Core
Related links: PowerPC Cores

The IBM PowerPC 440 core is a 32-bit Book E CPU for use in custom logic applications. This licensable embedded core integrates a superscalar 7-stage pipeline, separate instruction and data caches, a JTAG port, trace FIFO, multiple timers and a memory management unit (MMU), plus optional L2 cache interface and FPU core, with 2.0 DMIPS/MHz performance. The core is available as a hard macro in the IBM premium process technologies including 130nm, and also as a fully synthesizable core that can be fabricated at multiple foundries. The 440 core can be integrated with peripheral and application-specific macro cores using the CoreConnectTM bus architecture to develop system-on-a-chip solutions. For more information on PowerPC Licensing, please click here.

(Click on column header to sort)
iDocumentsTypeDate
(mm/dd/yy)
JTAG TAP Controller with PowerPC 4xx CoresApplication Note09/26/12
Multiprocessor Interrupt Controller Data BookDatabook05/16/11
!Multiprocessor Interrupt Controller Errata NoticeErrata Notice10/25/10
PPC440x6 Embedded Processor CoreUser Guide09/29/10
!PowerPC 450FPU Embedded Processor Core Support ManualHardware Reference Manual11/17/09
!PowerPC 440H6V3 Embedded Processor Core Support ManualHardware Reference Manual09/18/09
!L2 Cache Controller for PPC440 for Cu-11Databook07/08/09
PPC440x6 and PPC464 Linux RequirementApplication Note05/08/09
!Universal Interrupt Controller (UIC) for Cu-65HPDatabook03/24/09
!L2 Cache Controller for PPC440 for Cu-08Databook03/17/09
!L2 Cache Controller for PPC440 (Cu-08)Summary Datasheet02/19/09
!L2 Cache Controller for PPC440 for Cu-08Errata Notice02/19/09
!L2 Cache Controller for PPC440 for Cu-11Errata Notice02/18/09
!PPC440x5 Embedded Processor Core Support ManualHardware Reference Manual11/15/08
Using the New PPC4xx Indexed DCR Access InstructionsApplication Note06/15/08
Optimized Code Using DSP Instructions for PowerPC 4xxApplication Note04/17/08
!PowerPC 440-S Processor Core Errata NoticeErrata Notice01/30/08
!PPC440H6V3 Core Errata NoticeErrata Notice01/29/08
Optimizing PowerPC 440 and PowerPC 464 Memory Copy RoutinesApplication Note01/18/08
!PPC440 FPU Core User's ManualUser Guide05/18/07
Universal Interrupt Controller (UIC) for Cu-08Summary Datasheet03/12/07
Universal Interrupt Controller (UIC) for Cu-08Databook03/12/07
Routing Debug halt and Trace Signals with Multi-PPC405 Core DesignsApplication Note02/27/07
!Universal Interrupt Controller (UIC) for Cu-08 Errata NoticeErrata Notice01/26/07
PowerPC 464 CPU Core Feature Differences vs. PowerPC 440Application Note01/05/07
!PPC440A4FPUV1 Errata NoticeErrata Notice12/07/06
!PPC440G5FPUV1 Errata NoticeErrata Notice12/07/06
!PPC450FPUA6V1 Errata NoticeErrata Notice12/07/06
!L2 Cache Controller for PPC440 Cu-11Summary Datasheet11/13/06
IBM PowerPC 440 Embedded CoreProduct Brief11/09/06
Multiprocessor Interrupt Controller (MPIC)Product Overview03/02/06
!PPC440H6 ErrataErrata Notice02/17/06
!PowerPC 440 FPU embedded processorProduct Overview01/23/06
!PPC440H6V1 CoreHardware Reference Manual01/20/06
!PPC440H6V2 CoreHardware Reference Manual01/16/06
!PPC440FPU CoreHardware Reference Manual11/18/05
!PPC440A4V3 Errata DocumentErrata Notice10/17/05
!PPC440G5V2 Errata DocumentErrata Notice10/17/05
!PPC440G5V3 Errata DocumentErrata Notice10/17/05
!PPC440 Auxilliary Processor UnitHardware Reference Manual09/16/05
!L2 Cache for PPC440Databook06/10/05
PPC440x4 CPU Core User's ManualUser Guide07/15/03
PPC440x5 CPU CoreUser Guide07/15/03
Understanding the MAC Instructions in the IBM PowerPC 440 Processor CoreApplication Note06/30/03
!PPC440x4 CoreHardware Reference Manual04/16/03
Writing High Performance Assembler Functions for the PowerPC 440 CoreApplication Note10/10/01
IBM PowerPC 440 Microprocessor Core Programming Model OverviewApplication Note10/04/01
PowerPC 440 CPU CoreWhite Paper09/01/99

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