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PowerPC 405 Embedded Cores
Related links: PowerPC Cores

The IBM PowerPC 405 core is a 32-bit RISC CPU for use in custom logic applications. This licensable embedded core integrates a scalar 5-stage pipeline, separate instruction and data caches, a JTAG port, trace FIFO, multiple timers and a memory management unit (MMU), with 1.52 DMIPS/MHz performance. The core is available as a hard macro in the IBM premium process technologies including 130nm, and also as a fully synthesizable core that can be fabricated at multiple foundries. The 405 core can be integrated with peripheral and application-specific macro cores using the CoreConnect(TM) bus architecture to develop system-on-a-chip solutions. For more information on PowerPC Licensing, please click here.

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IBM PowerPC 405 Embedded CoreProduct Brief11/09/06
PowerPC 405 CPU Core Product OverviewProduct Overview09/02/06
Multiprocessor Interrupt Controller (MPIC)Product Overview03/02/06
PowerPC 405 CPU CoreWhite Paper11/01/98
Universal Interrupt Controller (UIC) for Cu-08Summary Datasheet03/12/07
Multiprocessor Interrupt Controller Data BookDatabook05/16/11
Universal Interrupt Controller (UIC) for Cu-08Databook03/12/07
PowerPC 405-S Embedded Processor Core User's ManualUser Guide06/16/10
PowerPC 405-S Embedded Processor Core User's ManualUser Guide06/16/10
PowerPC 405 Processor CoreUser Guide01/28/05
JTAG TAP Controller with PowerPC 4xx CoresApplication Note09/26/12
Attaching PowerPC 405 Core to PLB Crossbar ArbiterApplication Note04/27/09
Optimized Code Using DSP Instructions for PowerPC 4xxApplication Note04/17/08
Routing Debug halt and Trace Signals with Multi-PPC405 Core DesignsApplication Note02/27/07
IBM PowerPC Embedded Environment - Architectural Specifications for IBM PowerPC Embedded ControllersSpecifications06/01/98

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