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Cell Broadband Engine
Related links: PowerPC

The first-generation Cell Broadband Engine (BE) processor is a multi-core chip comprised of a 64-bit Power Architecture processor core and eight synergistic processor cores, capable of massive floating point processing, optimized for compute-intensive workloads and broadband rich media applications. A high-speed memory controller and high-bandwidth bus interface are also integrated on-chip. The breakthrough multi-core architecture and ultra high-speed communications capabilities deliver vastly improved, real-time response, in many cases 10 times the performance of the latest PC processors. The Cell BE architecture is OS neutral and supports multiple operating systems simultaneously. Applications may range from a next generation of game systems with dramatically enhanced realism, to systems that form the hub for digital media and streaming content in the home, to systems used to develop and distribute digital content, to systems to accelerate visualization and supercomputing applications.

A comprehensive Cell Broadband Engine resource center is located at http://www.ibm.com/developer/power/cell

iCategories
IBM SDK for Multicore Acceleration 

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iDocumentsTypeDate
(mm/dd/yy)
Cell Broadband Engine CMOS SOI 90 nm Hardware Initialization GuideInstallation Guide11/30/07
Cell Broadband Engine CMOS SOI 65 nm Hardware Initialization GuideInstallation Guide06/08/07
PPU & SPU C/C++ Language Extension SpecificationSoftware Reference Manual08/25/08
SIMD Math Library Specification for Cell BESoftware Reference Manual07/18/08
SPE Runtime Management Library version1 to version2 Migration GuideSoftware Reference Manual10/19/07
PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual Version 2.07cSoftware Reference Manual10/26/06
PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual Version 2.07cSoftware Reference Manual10/26/06
Cell Broadband Engine Programming Handbook Including the PowerXCell 8i ProcessorProgrammer's Guide06/03/09
Cell BE Programming Handbook Including PowerXCell 8iProgrammer's Guide05/12/08
MFC Transfer Class ID Register Programming Application NoteApplication Note09/22/11
Preventing Synergistic Processor Element Indefinite Stalls Resulting from Instruction Depletion in the Cell Broadband Engine Processor for CMOS SOI 90 nmApplication Note02/26/07
Introduction to the Cell MicroprocessorArticle09/15/05
SPU Application Binary Interface SpecificationSpecifications07/18/08
SPU Assembly Language SpecificationSpecifications07/18/08
Cell Broadband Engine ArchitectureSpecifications10/11/07
Cell Broadband Engine RegistersSpecifications09/18/07
Cell BE Linux Reference Implementation ABI SpecificationSpecifications08/22/07
SPU Instruction Set ArchitectureSpecifications01/27/07
A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a Cell ProcessorArticle03/10/05
A Double-Precision Multiplier with Fine-Grained Clock-Gating Support for a First-Generation Cell ProcessorArticle03/10/05
A Streaming Processing Unit for a Cell ProcessorArticle03/10/05
The Design and Implementation of a First-Generation Cell ProcessorArticle03/10/05

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