Multiple page size support

The POWER5+ processor supports four virtual memory page sizes: 4 KB, 64 KB, 16 MB, and 16 GB. The IBM® Power Systems processor-based servers also support using 64 KB pages in segments with base page size 4 KB. AIX® uses this process to provide the performance benefits of 64 KB pages when useful or resorting to 4 KB pages where 64 KB pages would waste too much memory, such as allocated but not used by the application.

Using a larger virtual memory page size like 64 KB for an application’s memory can significantly improve the application's performance and throughput due to hardware efficiencies associated with larger page sizes. Using a larger page size can decrease the hardware latency of translating a virtual page address to a physical page address. This decrease in latency is due to improving the efficiency of hardware translation caches like a processor’s translation lookaside buffer (TLB). Because a hardware translation cache only has a limited number of entries, using larger page sizes increases the amount of virtual memory that can be translated by each entry in the cache. This increases the amount of memory that can be accessed by an application without incurring hardware translation delays.

While 16 MB and 16 GB pages are only intended for very high performance environments, 64 KB pages are considered general-purpose, and most workloads will likely see a benefit from using 64 KB pages rather than 4 KB pages.