16-Port asynchronous adapter hardware information

The system interface presents a 3-bit address and 8-bit data as well as control lines to the chip. Data from the system interface is serialized for transmission to an external device. The serial data may include a parity bit at the byte boundary. Conversely, data from an external device is deserialized for transmission to the system interface. This data may also include a parity bit, which can be optionally checked. As an option, the channel can operate in first-in-first-out (FIFO) mode.

In FIFO mode, up to 16 bytes can be buffered in both the transmitter and receiver. The serial interface uses start-stop protocol for both data transmission and reception. That is, each byte (plus parity bit) is framed by a start bit and stop bit, which allows synchronization on an individual character (byte) basis.

The DUART chip uses a 12.288 MHz oscillator to generate its internal timing to drive the transmitter and receiver logic. The channel supports full duplex operation. Eight DUART chips are implemented on each 16-port adapter.

Thirteen system-accessible registers are available. Programmable features on each channel include:

• Character length: 5,6, 7, or 8 bits
• Parity generation/detection: even, odd, or none
• Number of stop bits: 1, 1.5, or 2
• Enable/disable interrupts. Received data available
• Transmitter holding register empty
• Line status
• Overrun error
• Parity error
• Framing error
• Break.

The following table is a summary of port (device interface) characteristics for the adapters.