Table 1 shows the register contents on entry to the SYNAD routine for BDAM, BPAM, BSAM, and QSAM.
Register | Bits | Meaning |
---|---|---|
0 | 0-7 | Value to be added to the status indicator's address to provide the address of the first CCW (QSAM only). Value may be zero, meaning unavailable, if LBI is used. |
8-31 | Address of the associated data event control block for BDAM, BPAM, and BSAM unless bit 2 of register 1 is on; address of the status indicators shown in Figure 1 for QSAM. If bit 2 of register 1 is on, the failure occurred in CNTRL, POINT, or BSP and this field contains the address on an internal BSAM ECB. | |
1 | 0 | Bit is on for error caused by input operation. |
1 | Bit is on for error caused by output operation. | |
2 | Bit is on for error caused by BSP, CNTRL, or POINT macro instruction (BPAM AND BSAM only). | |
3 | Bit is on if error occurred during update of existing record or if error did not prevent reading of the record. Bit is off if error occurred during creation of a new record or if error prevented reading of the record. | |
4 | Bit is on if the request was nonvalid. The status indicators pointed to in the data event control block are not present (BDAM, BPAM, and BSAM only). | |
5 | Bit is on if a nonvalid character was found in paper tape conversion (BSAM and QSAM only). | |
6 | Bit is on for a hardware error (BDAM only). | |
7 | Bit is on if no space was found for the record (BDAM only). | |
8-31 | Address of the associated data control block. | |
2-13 | 0-31 | Contents that existed before the macro instruction was issued. |
14 | 0-7 | Reserved. |
8-31 | Return address. | |
15 | 0-31 | Address of the error analysis routine. |
Table 2 shows the register contents on entry to the SYNAD routine for BISAM.
Register | Bits | Meaning |
---|---|---|
0 | 0-7 | Reserved. |
8-31 | Address of the first of two sense bytes. (Sense information is valid only when associated with a unit check condition.) | |
1 | 0-7 | Reserved. |
8-31 | Address of the DECB. See Table 1. | |
2-13 | 0-31 | Contents that existed before the macro instruction was issued. |
14 | 0-7 | Reserved. |
8-31 | Return address. | |
15 | 0-7 | Reserved. |
8-31 | Address of the SYNAD exit routine. |
Table 3 shows the register contents on entry to the SYNAD routine for QISAM.
Register | Bits | Meaning |
---|---|---|
0 | 0 | Bit 0=1 indicates that bits 8-31 hold the address of the key in error (only set for a sequence error). If bit 0=1—address of key that is out of sequence. If bit 0=0—address of a work area. |
1-7 | Reserved. | |
8-31 | Address of a work area containing the first 16 bytes of the IOB (after an uncorrectable I/O error caused by a GET, PUT, or PUTX macro instruction; original contents destroyed in other cases). If the error condition was detected before I/O was started, register 0 contains all zeros. | |
1 | 0-7 | Reserved. |
8-31 | Address of the buffer containing the error record (after an uncorrectable I/O error caused by a GET, PUT, or PUTX macro instruction while attempting to read or write a data record; in other cases, this register contains 0). | |
2-13 | 0-31 | Contents that existed before the macro instruction was issued. |
14 | 0-7 | Reserved. |
8-31 | Return address. This address is either an address in the control program's CLOSE routine (bit 2 of DCBEXCD2 is on), or the address of the instruction following the expansion of the macro instruction that caused the SYNAD exit routine to be given control (bit 2 of DCBEXCD2 is off). | |
15 | 0-7 | Reserved. |
8-31 | Address of the SYNAD exit routine. |