PGM, SPER and SPR2 trace entries

These trace entries represent a program event:

A PGM trace entry is for a program interrupt
An SPER trace entry is for a PER event requested in a SLIP trap
An SPR2 trace entry is for a PER event requested in a SLIP trap, when the STDATA keyword is specified on the trap

PR ASID TCB-ADDR  IDENT CD/D PSW----- ADDRESS- UNIQUE-1 UNIQUE-2 UNIQUE-3  PSACLHS-  PSALOCAL PASD SASD TIMESTAMP-RECORD  CP
                                               UNIQUE-4 UNIQUE-5 UNIQUE-6  PSACLHSE-

pr home tcb-addr  PGM  code pgm-old- pswaddr-  ilc-code tea-----           psaclhs-  psalocal pasd sasd timestamp-------  CP
                            pgm-old- pswctrl-           tea-----           psaclhse- 
                                                                
pr home tcb-addr  SPER code pgm-old- pswaddr-  ilc-code          trap----  psaclhs-  psalocal pasd sasd timestamp-------  CP
                            pgm-old- pswctrl-  per-addH per-addL           psaclhse-
 
pr home tcb-addr  SPR2 code pgm-old- pswaddr-  var1     var2     var3      psaclhs-  psalocal pasd sasd timestamp-------  CP 
                            pgm-old- pswctrl-  var4     var5     spc-exc

PR

pr: Identifier of the processor that produced the TTE.

ASID

home: Home address space identifier (ASID) associated with the TTE.

TCB-ADDR

tcb-addr: Address of the task control block (TCB) for the current task or the work element block (WEB).

IDENT

The TTE identifier, as follows:

PGM: Program interruption. An asterisk (*) before PGM indicates an unusual condition. PGM trace entries for program interrupts that may be resolved are not flagged. If the program interrupt is not resolved, then a subsequent RCVY trace entry is created and flagged with an asterisk.
SPER: SLIP program event recording

CD/D

code for PGM entry: Program interruption code
code for SPER entry: PER number

PSW----- ADDRESS-

The z/Architecture® 128-bit old PSW appears on two lines:

pswaddr: Two words, containing the 64-bit address portion of the PSW
pswctrl: Two words, containing the 64-bit "control" portion of the PSW

UNIQUE-1/UNIQUE-2/UNIQUE-3

UNIQUE-4/UNIQUE-5/UNIQUE-6

ilc-code: Instruction length code and interruption code.
per-addH: high-order bits of the SLIP/PER status address.
per-addL: low-order bits of the SLIP/PER status address.
tea-----: Translation exception address. In the high-order bit, 0 indicates primary and 1 indicates secondary.
trap----: SLIP/PER trap identifier in the form ID=xxxx.
var1, var2, var3, var4, var5: Each contains one word of variable data as specified by the STDATA keyword.
spc-exc: The message SpaceExc if more than five words of variable data are requested in the STDATA keyword.

PSACLHS-

psaclhs-: String for the current lock held, from the PSACLHS field of the PSA.

PSACLHSE-

psaclhse-: Extended string for the current lock held, from the PSACLHSE field of the PSA.

PSALOCAL

psalocal: Locally locked address space indicator, from the PSALOCAL field of the PSA.

PASD

pasd: Primary ASID (PASID) at trace entry.

SASD

sasd: Secondary ASID (SASID) at trace entry.

TIMESTAMP-RECORD

timestamp-------: Time-of-day (TOD) clock value when system trace created the trace entry. The value is in the same format as the time stamp on the logrec data set records.

CP

The CP column contains 2 hex digits of the processor model dependent information, which is intended to identify the physical CP that made the trace entry. CP is only provided when formatting SYSTRACE under IPCS. CP is not provided for SYSUDUMP, SYSABEND, or SNAP.