The hardware uses a machine check interruption to tell the control
program that it has detected a hardware malfunction. Machine checks
vary considerably in their impact on software processing:
- Soft errors: Some machine checks notify software that
the processor detected and corrected a hardware problem that required
no software recovery action.
- Hard errors: Other hardware problems detected by a processor
require software-initiated action for damage repair. Hard errors also
require software recovery to verify the integrity of the process that
experienced the failure.
The machine check interrupt code (MCIC) in the PSA FLCMCIC field
describes the error causing the interrupt. An MCIC can have more than
one bit on to indicate more than one failing condition.
For a machine check, the system writes a logrec error record. The
error record contains the MCIC, except when:
- The LRBMTCKS bit in field LRBMTERM of the logrec buffer (LRB)
is ON to indicate that the machine check old PSW and the MCIC are
both zero.
- The LRBMTINV bit in field LRBMTERM is ON to indicate that the
machine check old PSW is nonzero but the MCIC is zero.
Hard errors cause FRR and ESTAE processing.
See z/Architecture® Principles
of Operation for a complete description of the MCIC.