CORE STATUS: HD=h  MT=mm  [MODE: CP=cn  zIIP=zin]                                                  
ID    ST    ID RANGE   VP ISCM  CPU THREAD STATUS
cId   wst   tIdL-tIdH  vp xxxx  tt
cId   wst   tIdL-tIdH  vp xxxx  tt
cId   wst   tIdL-tIdH  vp xxxx  tt
CPC ND = tttttt.nnn.mmm.pp.ssssssssss

CPC SI = tttt.nnnnnnnnnnnnnnnn.mmmmmmmmmmmmmmmm.pppp.ssssssssssssssss
         Model: oooooooooooooooo
CPC ID = ii
CPC NAME = cpc_name
CPC IS RUNNING AT dd% OF NORMAL EFFECTIVENESS
LP NAME = lp_na      LP ID = jj
CSS ID = cc
MIF ID = m


+ ONLINE    - OFFLINE    W WLM-MANAGED        
N NOT AVAILABLE          / MIXED STATE
C GENERAL PURPOSE PROCESSOR
[A SYSTEM Z APPLICATION ASSIST PROCESSOR]
I SYSTEM Z INTEGRATED INFORMATION PROCESSOR
CPC ND CENTRAL PROCESSING COMPLEX NODE DESCRIPTOR
CPC SI SYSTEM INFORMATION FROM STSI INSTRUCTION
CPC ID CENTRAL PROCESSING COMPLEX IDENTIFIER
CPC NAME CENTRAL PROCESSING COMPLEX NAME
LP  NAME LOGICAL PARTITION NAME
LP  ID LOGICAL PARTITION IDENTIFIER
CSS ID CHANNEL SUBSYSTEM IDENTIFIER
MIF ID MULTIPLE IMAGE FACILITY IMAGE IDENTIFER

h

Indicates whether the system is enabled for HIPERDISPATCH (Y) or not (N).

mm

The maximum MT mode that can be supported by both the hardware and this IPL of z/OS®.

cn

The MT mode for standard CP cores. This can be modified by using the MT_CP_MODE parameter in the IEAOPTxx member. For more information, see IEAOPTxx MT_CP_MODE in z/OS MVS Initialization and Tuning Reference.

zin

The MT mode for System z Integrated Information Processors. This can be modified by using the MT_ZIIP_MODE parameter in the IEAOPTxx member. For more information, see IEAOPTxx MT_ZIIP_MODE in z/OS MVS Initialization and Tuning Reference.

cId

The core identifier.

wst

The state of the core, with each letter representing a different state:

w

When the core is being managed by WLM, this will be “W”, otherwise it will be blank.

s

The status of the core, which can be one of the following:

• + indicates the core is online.
• - indicates the core is offline.
• / indicates the core is in a mixed state, because the core is online but the threads currently online are unexpected with the MT mode for this core type. This state can occur in certain system abnormal conditions. You can generally get out of this state by reconfiguring the core to its desired state. For more information, see IEAOPTxx MT_xxxx_MODE in z/OS MVS Initialization and Tuning Reference.
• N indicates the core is neither online nor able to be configured online.

t

The type of the core, which can be one of the following:

• (a blank) – the core is a standard CP.
• A – The core is a System z Application Assist Processor.
• I – The core is a System z Integrated Information Processor.

tIdL

The lowest CPU address of a thread that belongs to this core.

tIdH

The highest CPU address of a thread that belongs to this core.

v

The HIPERDISPATCH vertical-ness of the core:

• H – The core is classified as a vertical high core.
• M – The core is classified as a vertical medium core.
• L – The core is classified as a vertical low core.

p

Indicates whether the core is parked (P) or unparked (blank).

xxxx

The interrupt subclass mask for the core.

t

The state of each thread that belongs to this core. There are n visible thread states, where n = (tIdH-tIdL)+1 and is OS and model dependent. The CPU ID for the first thread is tIdL. The state can be one of the following:

• + indicates the thread is online due to the current MT mode for this core type.
• - indicates the thread is offline due to the current MT mode for this core type.
• N indicates the thread is offline and expected to be offline due to the current MT mode for this core type. For more information, see IEAOPTxx MT_xxxx_MODE in z/OS MVS Initialization and Tuning Reference.

CPC ND = tttttt.nnn.mmm.pp.ssssssssss

The central processing complex node descriptor, in EBCDIC, where:

tttttt

The type number.

nnn

The model number of the processor at the last IML/POR. Note that if the processor is concurrently upgraded to a new model, this number will not reflect the new model until the next processor IML/POR.

mmm

The manufacturer.

pp

The plant of manufacture.

ssssssssssss

The sequence number.

dd

The approximate percentage, in decimal, of the actual effectiveness compared to the normal effectiveness of the CPC.

Indicates that a reduction in the current capability of the central processing complex (CPC) has been detected.

CPC SI = text02

Where text02 is:

tttt.nnnnnnnnnnnnnnnn.mmmmmmmmmmmmmmmm.pppp.ssssssssssssssss
        Model: oooooooooooooooo

This is the system information from the STSI instruction, in EBCDIC, where:

tttt

The type number.

nnnnnnnnnnnnnnnn

The model-capacity identifier. Note that the model-capacity identifier is updated after a concurrent upgrade.

mmmmmmmmmmmmmmmm

The manufacturer.

pppp

The plant of manufacture.

ssssssssssssssss

The sequence code.

oooooooooooooooo

The model number.

Note: If the core is concurrently upgraded to a new model, the model number in field oooooooooooooooo will reflect the new model without a core IML/POR.

Note: The "Model:" line is displayed only if the model number oooooooooooooooo differs from the model number/model-capacity identifier nnnnnnnnnnnnnnnn.

CPC ID = ii

The central processing complex node identifier, in binary.

CPC NAME = cpc_name

The central processing complex name, in EBCDIC.

LP NAME = lp_na

The logical partition name, in EBCDIC.

LP ID = jj

The logical partition identifier, in binary.

CSS ID = cc

The logical channel subsystem identifier, in binary.

MIF ID = m

The multiple image facility identifier, in binary. The MIF ID appears only if you are running in LPAR mode.