z/OS MVS Programming: Extended Addressability Guide
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Coding instructions in AR mode

z/OS MVS Programming: Extended Addressability Guide
SA23-1394-00

As you write your AR mode programs, use the advice in this section.
  • Always remember that for an instruction that uses a GPR as a base register, the system uses the contents of the associated AR to identify the address/data space that contains the data that the GPR points to.
  • Use ARs only for data reference; do not use them with branching instructions.
  • Just as you do not use GPR 0 as a base register, do not use AR/GPR 0 for addressing.
  • You cannot use the following instructions when your program is in AR mode:
    • Move to primary — MVCP
    • Move to secondary — MVCS
    • Program transfer — PT
    • Basic program call — basic PC

Because ARs that are associated with index registers are ignored, when you code assembler instructions in AR mode, place the commas very carefully. In those instructions that use both a base register and an index register, the comma that separates the two values is very important.

Table 1 shows four examples of how a misplaced comma can change how the assembler resolves addresses on the load instruction.

Table 1. Base and index register addressing in AR mode
Instruction Address Resolution
L 5,4(,3) or L 5,4(0,3) There is no index register. GPR 3 is the base register. AR 3 indicates the address/data space.
L 5,4(3) or L 5,4(3,0) GPR 3 is the index register. Because there is no base register, data is fetched from the primary address space.
L 5,4(6,8) GPR 6 is the index register. GPR 8 is the base register. AR 8 indicates the address/data space.
L 5,4(8,6) GPR 8 is the index register. GPR 6 is the base register. AR 6 indicates the address/data space.
For the first two entries in Table 1:
  • In primary mode, the examples of the load instruction give the same result.
  • In AR mode, the data is fetched using different ARs. In the first entry, data is fetched from the address/data space represented by the ALET in AR 3. In the second entry, data is fetched from the primary address space (because AR/GPR 0 is not used as a base register).
For the last two entries in Table 1:
  • In primary mode, the last two examples of the load instruction give the same result.
  • In AR mode, the first results in a fetch from the address/data space represented by AR 8, while the second results in a fetch from the address/data space represented by AR 6.

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