Directives and intrinsic procedures

The following major categories of directives and intrinsic procedures are new to this release.

POWER8 intrinsic procedures for vector processing

The following vector intrinsic procedures are added:

The vector gather bits by bytes doubleword procedure
- VEC_GBB
The vector count leading zeros procedure
- VEC_CNTLZ
The vector population count procedure
- VEC_POPCNT
Extended vector logical operations procedures
- VEC_EQV
- VEC_NAND
- VEC_ORC
128-bit integer add and subtract procedures
- VEC_ADD_U128
- VEC_SUB_U128
- VEC_ADDE_U128
- VEC_SUBE_U128
- VEC_ADDC_U128
- VEC_SUBC_U128
- VEC_ADDEC_U128
- VEC_SUBEC_U128
- VEC_BPERM

The following intrinsic procedures are extended to support doubleword types:

Vector pack procedures
- VEC_PACK
- VEC_PACKS
- VEC_PACKSU
Vector unpack procedures
- VEC_UNPACKL
- VEC_UNPACKH
Vector add and subtract procedures
- VEC_ADD
- VEC_SUB
Vector max and min procedures
- VEC_MAX
- VEC_MIN
Vector shift and rotate procedures
- VEC_RL
- VEC_SL
- VEC_SR
- VEC_SRA
Vector compare procedures
- VEC_CMPGE
- VEC_CMPLE

POWER8 cryptography intrinsic procedures

The following intrinsic procedures are provided to perform cryptographic operations:

Advanced Encryption Standard (AES) procedures
- VCIPHER
- VCIPHERLAST
- VNCIPHER
- VNCIPHERLAST
- VSBOX
Secure Hash Algorithm (SHA) procedures
- VSHASIGMAD
- VSHASIGMAW
Miscellaneous procedures
- VPMSUMB
- VPMSUMH
- VPMSUMW
- VPMSUMD
- VPERMXOR

POWER8 transactional memory intrinsic procedures

Transactional memory is a model for parallel programming. In this model, you can designate a block of instructions or statements to be treated atomically.

The transactional_memory module provides the following intrinsic procedures to work with transactions:

Transaction begin and end procedures
- TM_BEGIN
- TM_END
- TM_SIMPLE_BEGIN
Transaction abort procedures
- TM_ABORT
- TM_NAMED_ABORT
Transaction inquiry procedures
- TM_FAILURE_ADDRESS
- TM_FAILURE_CODE
- TM_IS_CONFLICT
- TM_IS_FAILURE_PERSISTENT
- TM_IS_FOOTPRINT_EXCEEDED
- TM_IS_ILLEGAL
- TM_IS_NAMED_USER_ABORT
- TM_IS_NESTED_TOO_DEEP
- TM_IS_USER_ABORT
- TM_NESTING_DEPTH

POWER8 prefetch directives

The following directives display the problem state control of the Data Stream Control Register (DSCR) in an intuitive, portable, and optimization-friendly way:

Transient attribute enable directives
- HARDWARE_TRANSIENT_ENABLE
- LOAD_TRANSIENT_ENABLE
- SOFTWARE_TRANSIENT_ENABLE
- STORE_TRANSIENT_ENABLE
Unit count enable and set directives
- HARDWARE_UNIT_COUNT_ENABLE
- SET_PREFETCH_UNIT_COUNT
- SOFTWARE_UNIT_COUNT_ENABLE
Prefetch depth directives
- DEFAULT_PREFETCH_DEPTH
- DEPTH_ATTAINMENT_URGENCY
Load stream enable and disable directives
- LOAD_STREAM_DISABLE
- STRIDE_N_STREAM_ENABLE

POWER8 prefetch intrinsic procedures

You can use the following intrinsic procedures to get or set the value of the DSCR:

PREFETCH_GET_DSCR_REGISTER
PREFETCH_SET_DSCR_REGISTER

Note: POWER8™ directives and intrinsic procedures are valid only when -qarch is set to target POWER8 processors.

For more information about the directives and intrinsic procedures, see Hardware-specific directives, Hardware-specific intrinsic procedures (IBM extension), Vector intrinsic procedures (IBM extension), or The TRANSACTIONAL_MEMORY intrinsic module (IBM extension).

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