Support for POWER8 processors

XL Fortran for AIX®, V15.1 supports POWER8™ processors.

The new features and enhancements introduced in support of the POWER8 processors, fall under the following categories:

Mathematical Acceleration Subsystem (MASS) libraries for POWER8 processors

Scalar libraries
The MASS library interfaces include the following features:
  • The scalar functions have generic interfaces that can be called with REAL(4) or REAL(8) arguments.
  • The scalar functions are marked pure. You can call them from pure procedures.
  • The scalar functions are marked elemental. You can call them with an array argument and apply them to all the array elements.
  • The intent of the argument is specified to assist in compiler error checking.

For more information about the scalar libraries, see Using the scalar library.

Vector libraries

The vector MASS library libmassvp8.a contains vector procedures that have been tuned for the POWER8 architecture. The procedures can be used in either 32-bit mode or 64-bit mode.

The MASS vector library interfaces include the following features:
  • The vector functions have generic interfaces that can be called with REAL(4) or REAL(8) arguments.
  • The vector functions are marked pure. You can call them from pure procedures.
  • The intent of the argument is specified to assist in compiler error checking.

For more information about the vector libraries, see Using the vector libraries.

SIMD libraries

The MASS SIMD library libmass_simdp8.a contains an accelerated set of frequently used math intrinsic procedures that provide improved performance over the corresponding standard system library procedures.

The MASS SIMD library interfaces include the following features:
  • The SIMD functions are marked pure. You can call them from pure procedures.
  • The intent of the argument is specified to assist in compiler error checking.

For more information about the SIMD libraries, see Using the SIMD libraries.

Compiler options for POWER8 processors

The -qarch compiler option specifies the processor architecture for which code is generated. The -qtune compiler option tunes instruction selection, scheduling, and other architecture-dependent performance enhancements to run best on a specific hardware architecture.

The new -qarch=pwr8 suboption produces object code containing instructions that will run on the POWER8 hardware platforms. With the new -qtune=pwr8 suboption, optimizations are tuned for the POWER8 hardware platforms.

For more information, see -qarch and -qtune.

Hardware directives and intrinsics for POWER8 processors

New hardware directives and intrinsics are added to support the following POWER8 processor features:
  • POWER8 intrinsics for vector processing
  • POWER8 cryptography intrinsics
  • POWER8 transactional memory intrinsics
  • POWER8 prefetch directives
  • POWER8 prefetch intrinsic procedures

For more information about the directives and intrinsic procedures, see Hardware-specific directives, Hardware-specific intrinsic procedures (IBM extension), Vector intrinsic procedures (IBM extension), or The TRANSACTIONAL_MEMORY intrinsic module (IBM extension).

Parent topic: What's new for IBM XL Fortran for AIX, V15.1