The IBM PowerPC 440 core is a 32-bit Book E CPU for use in custom logic applications. This licensable embedded core integrates a superscalar 7-stage pipeline, separate instruction and data caches, a JTAG port, trace FIFO, multiple timers and a memory management unit (MMU), plus optional L2 cache interface and FPU core, with 2.0 DMIPS/MHz performance. The core is available as a hard macro in the IBM premium process technologies including 130nm, and also as a fully synthesizable core that can be fabricated at multiple foundries. The 440 core can be integrated with peripheral and application-specific macro cores using the CoreConnectTM bus architecture to develop system-on-a-chip solutions. For more information on PowerPC Licensing, please click here.

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	Documents	Type	Date (mm/dd/yy)
	PPC440x6 Embedded Processor Core	User Guide	07/21/08
	Using the New PPC4xx Indexed DCR Access Instructions	Application Note	06/15/08
	Optimized Code Using DSP Instructions for PowerPC 4xx	Application Note	04/17/08
	Optimizing PowerPC 440 and PowerPC 464 Memory Copy Routines	Application Note	01/18/08
	Universal Interrupt Controller (UIC) for Cu-08	Summary Datasheet	03/12/07
	Universal Interrupt Controller (UIC) for Cu-08	Databook	03/12/07
	Routing Debug halt and Trace Signals with Multi-PPC405 Core Designs	Application Note	02/27/07
	PowerPC 464 CPU Core Feature Differences vs. PowerPC 440	Application Note	01/05/07
	Multiprocessor Interrupt Controller	Databook	03/03/06
	Porting Applications to the IBM eServer Blue Gene/L System Solution	Application Note	04/18/05
	PowerPC 4XX CPU Core FAQ	FAQ	12/23/04
	PowerPC 440x5 CPU Core	User Guide	07/15/03
	PPC440x4 CPU Core User's Manual	User Guide	07/15/03
	Understanding the MAC Instructions in the IBM PowerPC 440 Processor Core	Application Note	06/30/03
	Writing High Performance Assembler Functions for the PowerPC 440 Core	Application Note	10/10/01
	IBM PowerPC 440 Microprocessor Core Programming Model Overview	Application Note	10/04/01
	PowerPC 440 CPU Core	White Paper	09/01/99