The IBM PowerPC 405 core is a 32-bit RISC CPU for use in custom logic applications. This licensable embedded core integrates a scalar 5-stage pipeline, separate instruction and data caches, a JTAG port, trace FIFO, multiple timers and a memory management unit (MMU), with 1.52 DMIPS/MHz performance. The core is available as a hard macro in the IBM premium process technologies including 130nm, and also as a fully synthesizable core that can be fabricated at multiple foundries. The 405 core can be integrated with peripheral and application-specific macro cores using the CoreConnect(TM) bus architecture to develop system-on-a-chip solutions. For more information on PowerPC Licensing, please click here.

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	Documents	Type	Date (mm/dd/yy)
	Optimized Code Using DSP Instructions for PowerPC 4xx	Application Note	04/17/08
	PPC405-S Embedded Processor Core User's Manual	User Guide	07/18/07
	Universal Interrupt Controller (UIC) for Cu-08	Summary Datasheet	03/12/07
	Universal Interrupt Controller (UIC) for Cu-08	Databook	03/12/07
	Routing Debug halt and Trace Signals with Multi-PPC405 Core Designs	Application Note	02/27/07
	PowerPC 405 CPU Core Product Overview	Product Overview	09/02/06
	Multiprocessor Interrupt Controller	Databook	03/03/06
	PowerPC 405 Processor Core	User Guide	01/28/05
	PowerPC 4XX CPU Core FAQ	FAQ	12/23/04
	PowerPC 405 CPU Core	White Paper	11/01/98
	IBM PowerPC Embedded Environment - Architectural Specifications for IBM PowerPC Embedded Controllers	Specifications	06/01/98