The first-generation Cell Broadband Engine (BE) processor is a multi-core chip comprised of a 64-bit Power Architecture processor core and eight synergistic processor cores, capable of massive floating point processing, optimized for compute-intensive workloads and broadband rich media applications. A high-speed memory controller and high-bandwidth bus interface are also integrated on-chip. The breakthrough multi-core architecture and ultra high-speed communications capabilities deliver vastly improved, real-time response, in many cases 10 times the performance of the latest PC processors. The Cell BE architecture is OS neutral and supports multiple operating systems simultaneously. Applications may range from a next generation of game systems with dramatically enhanced realism, to systems that form the hub for digital media and streaming content in the home, to systems used to develop and distribute digital content, to systems to accelerate visualization and supercomputing applications.

A comprehensive Cell Broadband Engine resource center is located at http://www.ibm.com/developer/power/cell

	Categories
	IBM SDK for Multicore Acceleration

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	Documents	Type	Date (mm/dd/yy)
	Cell BE Programming Handbook Including PowerXCell 8i	Programmer's Guide	05/12/08
	Cell Broadband Engine CMOS SOI 90 nm Hardware Initialization Guide	Installation Guide	11/30/07
	SPE Runtime Management Library	Software Reference Manual	10/19/07
	SPE Runtime Management Library version1 to version2 Migration Guide	Software Reference Manual	10/19/07
	Cell BE Programming Tutorial	Programmer's Guide	10/19/07
	Cell Broadband Engine Architecture	Specifications	10/11/07
	Cell Broadband Engine Registers	Specifications	09/18/07
	PPU & SPU C/C++ Language Extension Specification	Software Reference Manual	09/14/07
	SIMD Math Library Specification for Cell BE	Software Reference Manual	09/14/07
	SPU Application Binary Interface Specification	Specifications	09/03/07
	SPU Assembly Language Specification	Specifications	09/03/07
	Cell BE Linux Reference Implementation ABI Specification	Specifications	08/22/07
	Cell Broadband Engine CMOS SOI 65 nm Hardware Initialization Guide	Installation Guide	06/08/07
	SPE Runtime Management Library	Software Reference Manual	03/08/07
	Preventing Synergistic Processor Element Indefinite Stalls Resulting from Instruction Depletion in the Cell Broadband Engine Processor for CMOS SOI 90 nm	Application Note	02/26/07
	SPU Instruction Set Architecture	Specifications	01/27/07
	PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual Version 2.07c	Software Reference Manual	10/26/06
	A Programming Example: Large Fast Fourier Transform on the Cell Broadband Engine	White Paper	10/31/05
	Cell Broadband Engine Support for Privacy, Security, and Digital Rights Management Applications	White Paper	10/31/05
	H.264 Video Encoding Algorithm on Cell Broadband Engine	White Paper	10/31/05
	Introduction to the Cell Broadband Engine	White Paper	10/31/05
	Terrain Rendering Engine (TRE): Cell Broadband Engine Optimized Real-time Ray-caster	White Paper	10/31/05
	Introduction to the Cell Microprocessor	Article	09/15/05
	A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a Cell Processor	Article	03/10/05
	A Double-Precision Multiplier with Fine-Grained Clock-Gating Support for a First-Generation Cell Processor	Article	03/10/05
	A Streaming Processing Unit for a Cell Processor	Article	03/10/05
	The Design and Implementation of a First-Generation Cell Processor	Article	03/10/05
	Microprocessor Report - Cell Moves into the Limelight	Analyst Report	02/14/05
	Microprocessor Reports - 2004 Technology Awards	Analyst Report	01/31/05